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MAX2769
Universal GPS Receiver
Pin Description
10
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
—
NAME
ANTFLAG
LNAOUT
ANTBIAS
VCCRF
MIXIN
LD
SHDN
SDATA
SCLK
CS
VCCVCO
CPOUT
VCCCP
VCCD
XTAL
CLKOUT
Q1
Q0
VCCADC
I0
I1
N.C.
VCCIF
IDLE
LNA2
PGM
LNA1
N.C.
EP
FUNCTION
Active Antenna Flag Logic Output. A logic-high indicates that an active antenna is connected to the
ANTBIAS pin.
LNA Output. The LNA output is internally matched to 50 Ω .
Buffered Supply Voltage Output. Provides a supply voltage bias for an external active antenna.
RF Section Supply Voltage. Bypass to GND with 100nF and 100pF capacitors in parallel as close as
possible to the pin.
Mixer Input. The mixer input is internally matched to 50 Ω .
Lock-Detector CMOS Logic Output. A logic-high indicates the PLL is locked.
Operation Control Logic Input. A logic-low shuts off the entire device.
Data Digital Input of 3-Wire Serial Interface
Clock Digital Input of 3-Wire Serial Interface. Active when CS is low. Data is clocked in on the rising
edge of the SCLK.
Chip-Select Logic Input of 3-Wire Serial Interface. Set CS low to allow serial data to shift in. Set CS high
when the loading action is completed.
VCO Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin.
Charge-Pump Output. Connect a PLL loop filter as a shunt C and a shunt combination of series R and
C (see the Typical Application Circuit ).
PLL Charge-Pump Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the
pin.
Digital Circuitry Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin.
XTAL or Reference Oscillator Input. Connect to XTAL or a DC-blocking capacitor if TCXO is used.
Reference Clock Output
Q-Channel Voltage Outputs. Bits 0 and 1 of the Q-channel ADC output or 1-bit limited differential logic
output or analog differential voltage output.
ADC Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin.
I-Channel Voltage Outputs. Bits 0 and 1 of the I-channel ADC output or 1-bit limited differential logic
output or analog differential voltage output.
No Connection. Leave this pin unconnected.
IF Section Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin.
Operation Control Logic Input. A logic-low enables the idle mode, in which the XTAL oscillator is active,
and all other blocks are off.
LNA Input Port 2. This port is typically used with an active antenna. Internally matched to 50 Ω .
Logic Input. Connect to GND to use the serial interface. A logic-high allows programming to 8 hard-
coded by device states connecting SDATA, CS , and SCLK to supply or ground according to Table 3.
LNA Input Port 1. This port is typically used with a passive antenna. Internally matched to 50 Ω (see the
Typical Application Circuit ).
No connection. Leave this pin open.
Exposed Paddle. Ultra-low-inductance connection to ground. Place several vias to the PCB ground
plane.
Maxim Integrated
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